A. Field of the Invention
The invention relates to integrated circuit construction, and more particularly to an integrated circuit boundary or edge construction and method of assembly.
B. Prior Art
In the construction of integrated circuits, it is customary that tens, or more typically hundreds, of integrated circuits are produced on a single circular wafer of silicon, usually two, three or four inches in diameter. Each integrated circuit is rectangular, having a dimension on the order of one quarter inch on a side. Between integrated circuits is a scribing line, where a diamond saw or diamond scribe or laser scribe cuts the wafer into individual integrated circuits known as die. In each wafer, there are some dice which do not operate properly. The percentage of operable circuits per wafer determine the yield of the manufacturing process. To increase productivity, it is desirable to enhance yield.
Besides the problem of yield, another problem of concern to integrated circuit manufacturers is the reliability of packaged circuits. The dice, once they are cut from a wafer, are mounted on ceramic or metal substrates and covered with a ceramic or plastic housing. For example, when a ceramic housing is provided, known as "cerdip" package, an acronym for "ceramic dual-in-line" package, one process requires high temperature to achieve proper sealing of the housing to the substrate which holds the integrated circuit. Typically, a sealing temperature of 480.degree. C. for approximately nine minutes is used. Such a high temperature enhances ion mobility from lateral edges to within or near the integrated circuit, sometimes causing contaminant ions lodged along the scribing line to be injected into active portions of the integrated circuit, somewhat resembling an unwanted process step wherein contaminants migrate into the circuit. This migration is not limited to high temperature seals or particular package types, but occurs to an extent in all packages.
Previously, the lateral edges of the integrated circuit included exposed layers of oxide and perhaps other materials and the interfaces between these layers which were transparent to mobile ions and other contaminants which could migrate into active areas of the circuit.
In certain prior art integrated circuit constructions channel guards have been used to isolate active circuit areas, as in U.S. Pat. Nos. 3,808,058 and 3,559,283. Also, glass layers have been used to encapsulate integrated circuits, as in U.S. Pat. No. 3,706,129. Also, barriers to retard field inversions have been provided. Yet none of these structures adequately stops contaminant migration.
It is our object to increase integrated circuit chip reliability by decreasing failure modes due to ion migration from within or upon scribe line areas into active circuit regions and perhaps other causes. Another object is to improve the yield of operable integrated circuits cut from a wafer.